1. Field of the Invention
The present invention relates generally to Analog to Digital (A/D) converters and converting methods, and more particularly to two stage parallel type converters which use the first stage of conversion to determine the coarse range of the input voltage and a second stage to resolve the fine increment of the input voltage. The present invention has applicability to video and digital signal processing.
2. Description of the Background Art
The application of digital processing and transmission methods to analog information requires a technique for the conversion of signals from their analog form to a digital representation. Well known types of A/D converters include the Successive Approximation type which produces a digital output using a digital to analog converter to create successive trial and error approximations of the input, and the parallel comparator type or FLASH converter, which compares multiple voltage references to the input voltage and outputs from the encoding logic the digital code representing the voltage reference closest to the input voltage in one operation. FIG. 1 shows a representation of the FLASH type of A/D Converter. Typically the output is a binary code that is constructed in the Encoder Logic 30 thus providing an n bit resolution of the input signal. This structure typically requires 2.sup.n voltage references 10 and 2.sup.n comparators 20. As the resolution of this type of converter is improved (the number of output bits increases), the design becomes unwieldy.
In order to simplify the design of the FLASH A/D Converter, two techniques are known. In beth techniques multiple stages of conversion are used accomplish the A/D conversion. In the first technique, as shown in U.S. Pat. No. 5,302,869 (issued Apr. 12, 1994 to Hosotani et al. for a "Voltage Comparator and Subranging A/D Converter Including Such Voltage Comparator"), U.S. Pat. No. 5,389,929 (issued Feb. 14, 1995 to Nayebi et al. for a "Two-Step Subranging Analog-To-Digital Converter"), U.S. Pat. No. 5,353,027 (issued Oct. 4, 1994 to Vorenkamp et al. for a "Multistep Analog-To-Digital Converter With Error Correction"), U.S. Pat. No. 5,369,309 (issued Nov. 29, 1994 to Bacrania et al. for an "Analog-To-Digital Converter and Method of Fabrication"), and U.S. Pat. No. 5,387,914 (issued Feb. 7, 1995 to Mangelsdorf for a "Correction Range Technique for Multi-Range A/D Converter"), the first stage is a coarse resolution FLASH A/D conversion and the second stage, with a Digital to Analog Converter, adjusts the voltage references of the voltage comparators to form a fine resolution conversion. The results of the two conversions are encoded to form the digital output word representing the magnitude of the analog input voltage. In the second technique, as shown in U.S. Pat. No. 5,291,198 (issued Mar. 1, 1994 to Dingwall et al. for an "Averaging Flash Analog-To-Digital Converter"), U.S. Pat. No. 5,223,836 (issued Jun. 29, 1993 to Komatsu for a "Subranging Analog-To-Digital Converter With Priority Weighted Correction for the M.S.B. Group"), U.S. Pat. No. 5,400,029 (issued to Kobayashi for an "Analog-Digital Converter Circuit Device and Analog-Digital Conversion Method"), U.S. Pat. No. 4,733,217 (issued Mar. 22, 1988 to Dingwall for a "Subranging Analog-To-Digital Converter"), U.S. Pat. No. 5,349,354 (issued Sep. 20, 1994 to Ho et al. for an "A/D Converter And Converting Method Having Coarse Comparison And Fine Comparison Periods"), there will be multiple conversion stages with voltage references being appropriately switch to each stage by decision logic based on the results of the previous comparison stages.
As an example of the second techniques of multiple stage conversion, see in FIG. 2., which is a schematic diagram of U.S. Pat. No. 4,903,028 (issued Feb. 20, 1990 to N. Fukashima for an "Analog to Digital Converter"), that by creating a set of voltage sources 1 that have incrementally increasing values from V.sub.REFBOT (the lowest value) to V.sub.REFTOP (the highest value) establishes the range of conversion of the voltage input (V.sub.in). A set of Coarse Subranging Comparators 2 are connected to the voltage input and to the set of voltage reference at discrete intervals establishing the course subranges 1a,1b of V.sub.in. The output of the Coarse Subrange Comparators 5 is the input to a Steering Logic and Switch Unit 3 that places a set of Fine Subrange Comparators 4 at the appropriate Subrange of the Voltage Reference Set 1. The set of Voltage References 1a are divided into fine increments establishing the maximum resolution of the conversion of V.sub.in to Digital Output {D0, D1, D2, . . . , Dn}. As V.sub.in changes the value of the output codes or the Coarse Subrange Comparators 5 change and the Steering Logic and Switch Unit 3 moves the Fine Subrange Comparators 4 to the next subrange (from 1a to 1b).
Due to the tolerances in component selection and process variation, the Output Codes 5 of the Coarse Subrange Comparators 2 may be in error. To detect this error, there will be Extra Fine Subrange Comparators 4a&4b that will be placed above and below the subrange 1a or 1b determined by V.sub.in. The output of the Extra Fine Comparators 4a&4b form an error code 7. The output codes for Fine Subrange Comparators 6, the set of error codes 7, and the set of Coarse Subrange Codes 5 are interpreted by the Output Encoding Logic 8 to determine the output digital representation {D0, D1, D2, . . . , Dn}. of the voltage input V.sub.in.